Ders Adı İleri VSLI sistem Tasarımı 536
Semester Güz
Ders Tipi Zorunlu
Teori 3
Kredi 3
ECTS 10
Dersin Açıklaması
Front-End Digital Design: Hardware Description Language (VHDL), Register Transfer Level (RTL) Design, RTL Verification, Gate Level Simulation, Standard Delay Format(SDF), Unix, Cadence ncsim simulator,
hierarchical RTL, Logic Synthesis and Optimization, Static Timing Analysis (STA), Design For Test (DFT), Automatic Test Pattern Generation (ATPG), Scan Insertion, Boundary Scan Cells, Built In Self
Test (BIST)
Subsystem design: Combinational Logic, Flip-Flops, Shift Registers, Finite State Machines (FSM), Clock Dividers, Adders, Multipliers, Multiplexers, Decoder/Encoders, Counters, Tri-state/Bidirectional
Buffers, RAM/ROM memories, ALU, Processors, FIFOs, Controllers, Converters, Frequency Dividers